This application claims the priority benefit of Taiwan application serial no. 92205531, filed Apr. 9, 2003.
1. Field of Invention
The present invention relates to a package substrate, and more particularly, to a flip-chip package substrate having a better electrical performance.
2. Description of Related Art
High speed, high quality, and more versatile products are being pursued by current information society. Product appearance has developed along the trend of lighter, thinner, shorter, and smaller. The general electronic product has a semiconductor chip and a substrate connected to the semiconductor chip, and the semiconductor chip receives a signal from a motherboard or outside, or transmits the signal to the motherboard or outside via a transmission circuit of the substrate. Therefore, the signal transmission quality of the substrate significantly impacts the operation process of the semiconductor chip.
However, the signal transmission quality of the substrate is impacted by the circuit layout of the substrate as shown below. FIG. 1 schematically shows a sectional view of a conventional flip-chip package structure. FIG. 2 schematically shows a partial magnified top view of the substrate traces in FIG. 1. Referring to FIG. 1, the substrate 110 comprises a plurality of bump pads 112 and a plurality of solder-ball pads 122, wherein the bump pads 112 are disposed on a first surface 114 of the substrate 110, and the solder-ball pads 122 are disposed on a second surface 124 of the substrate 110. The bump pads 112 are electrically connected to the solder-ball pads 122 via an internal circuit (not shown) of the substrate 110. A chip 130 is joined to the bump pads 112 of the substrate 110 and electrically connected to the substrate 110 via multiple bumps 132. An underfill 140 is dispensed between the chip 130 and the substrate 110 so as to cover the bumps 132. Multiple solder balls 150 are disposed on the solder-ball pads 122. The substrate 110 is electrically connected to an external circuit (not shown) via the solder balls 150, so that the chip 130 can transmit signal to the external circuit.
Referring to both FIG. 1, and FIG. 2, the region on which the solder-ball pads are laid out is generally divided into a core solder-ball-pad layout region 126 and a peripheral solder-ball-pad layout region 128, wherein the core solder-ball-pad layout region 126 is disposed on the central area of the second surface 124 of the substrate 110. The solder-ball pad peripheral layout region 128 surrounds the periphery of the core solder-ball-pad layout region 126. Both the core solder-ball-pad layout region 126 and the peripheral solder-ball-pad layout region 128 have solder-ball pads 122 disposed on them. Generally speaking, the solder-ball pads, 122 disposed on the core solder-ball-pad layout region 126 are either used as the power/grounding or without any electrical function. The solder-ball pads 122 for transmitting signals (e.g. the solder-ball pads marked as xe2x80x9c1xe2x80x9d in FIG. 2), the solder-ball pads for connecting the power plane (e.g. the solder-ball pads marked as xe2x80x9c2xe2x80x9d in FIG. 2), the solder-ball pads for connecting the ground plane (e.g. the solder-ball pads marked as xe2x80x9c3xe2x80x9d in FIG. 2), and the solder-ball pads having no electrical function are randomly distributed on the peripheral solder-ball-pad layout region 128. As mentioned above, the solder-ball pads used for transmitting signals are all disposed on the peripheral solder-ball-pad layout region 128.
Referring to FIG. 2, the chip 130 transmits signals via the traces fanned out to the peripheral region of the substrate 110 and the traces inside the via holes 113. The bumps 112 are electrically connected to the solder-ball pads 122 for transmitting signals (e.g. the solder-ball pads marked as xe2x80x9c1xe2x80x9d in FIG. 2) via the traces 111 and the traces inside the via holes 113. The chip 130 has a centerline 134, which divides the chip 130 into two equal parts. Since the traces layout area neighboring the centerline 134 of the chip 130 is rather small, the traces (e.g. traces 111a, 111b, 111c, 111d, 111e, and 111f) neighboring the centerline 134 of the chip 130 have to extend in a rather long distance and parallelly to the centerline 134 of the chip 130. The pitch p between the neighboring traces 111a, 111b, 111c, 111d, 111e, and 111f in the parallel arranged section is too short, and if the signal is transmitted via the traces 111a, 111b, 111c, 111d, 111e, and 111f, more noise may be generated and the electrical performance is deteriorated.
It is one of the objects of the present invention to provide a substrate, in which a bigger pitch between the traces neighboring to the centerline of the chip is provided, so as to improve the electrical performance.
In order to achieve the object mentioned above, the substrate has a first surface and a corresponding second surface. The chip is adapted to be disposed on the first surface of the substrate and electrically connected to the substrate. The chip has a centerline, which evenly divides the chip into two equal parts. The substrate has a peripheral connection-pad layout region disposed on the second surface of the substrate. The peripheral connection-pad layout region has a centerline neighboring region which the centerline of the chip traverses. The substrate also has a plurality of central connection pads disposed in the centerline neighboring region.
In accordance with a preferred embodiment of the present invention, within the centerline neighboring region, at both sides of the centerline of the chip is respectively lined with the central connection pads in three rows. The central connection pads in each row are lined in parallel to the direction extending the centerline. The centerline traverses between the central connection pads arranged in two neighboring rows. The ratio of the number of the central connection pads for transmitting signals to the total number of the central connection pads is equal to or less than {fraction (2/7)}.
In accordance with a preferred embodiment of the present invention, within the centerline neighboring region, the central connection pads are lined in five rows. The central connection pads in each row are lined in parallel to the centerline. The centerline traverses the central connection pads arranged in a central row. The ratio of the number of the central connection pads for transmitting signals to the total number of the central connection pads is less than {fraction (2/7)}.
In summary, since the central connection pads for transmitting signals disposed in the centerline neighboring region are relatively few, the multiple traces neighboring the centerline of the chip do not extend in a rather long distance and parallelly to the centerline. Instead, they only extend parallelly in a short distance and then extend gradually increasing the pitch between the neighboring traces. Therefore, the cross-talk generated between the traces is reduced and the noise generated by signal transmission on the traces is also dramatically diminished.